module reg_group(
        input we,
        input clk,
        input [1:0]sr,
        input [1:0]dr,
        input [7:0]i,
        output reg [7:0]s,
        output reg [7:0]d
        );
        reg [7:0] R0,R1,R2,R3;
            
initial
begin
R0=8'b0000_0001;
R3=8'b0000_0111;
end            
            
always@ (*)        
begin
     case(sr[1:0])
        2'b00: s=R0;
        2'b01: s=R1;
        2'b10: s=R2;
        2'b11: s=R3;
        endcase
end

always@ (*)        
begin
    case(dr[1:0])
        2'b00: d=R0;
        2'b01: d=R1;
        2'b10: d=R2;
        2'b11: d=R3;
        endcase
end

always@ (negedge clk)        
begin
    if(we==1 && dr == 2'b00)R0<=i;
    else if(we==1 && dr == 2'b01)R1<=i;
    else if(we==1 && dr == 2'b10)R2<=i;
    else if(we==1 && dr == 2'b11)R3<=i;
    else ;
end
endmodule        
        